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(Referência obtida automaticamente do Web of Science, por meio da informação sobre o financiamento pela FAPESP e o número do processo correspondente, incluída na publicação pelos autores.)

Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors

Texto completo
Autor(es):
Trevisoli, Renan [1] ; Doria, Rodrigo Trevisoli [2] ; Barraud, Sylvain [3] ; Pavanello, Marcelo Antonio [2]
Número total de Autores: 4
Afiliação do(s) autor(es):
[1] Univ Fed ABC, CECS, Ave Estados 5001, BR-09210580 Santo Andre - Brazil
[2] Ctr Univ FEI, Dept Elect Engn, Av Humberto de Alencar Castelo Branco 3972, BR-09850901 Sao Bernardo Do Campo - Brazil
[3] Univ Grenoble Alpes, CEA, LETI, Minatec Campus, F-38054 Grenoble - France
Número total de Afiliações: 3
Tipo de documento: Artigo Científico
Fonte: MICROELECTRONIC ENGINEERING; v. 215, JUL 15 2019.
Citações Web of Science: 0
Resumo

The aim of this work is to propose a semi-analytical model for the low frequency noise caused by interface traps in Triple-Gate Junctionless Nanowire Transistors. The proposed model is based on a drain current model, which includes short channel effects influence. The surface potential and the occupied trap density equations are solved self consistently to obtain the traps influence in the static drain current, which is used to determine the trap related noise. In this work, the low frequency noise of traps in discrete levels is analyzed. The model has been validated with 3D simulations considering different devices characteristics, biases and trap levels. Experimental results have also been used to demonstrate the model suitability. (AU)

Processo FAPESP: 14/18041-8 - Caracterização elétrica e modelagem de dispositivos eletrônicos avançados
Beneficiário:Renan Trevisoli Doria
Linha de fomento: Bolsas no Brasil - Pós-Doutorado