On the Application of Junctionless Nanowire Transistors in Basic Analog Building Blocks

In this work an evaluation of analog building blocks using junctionless nanowire transistors is presented. This analysis has been carried out through experimental measurements of junctionless nMOS transistors configured as two amplifier stages composed by single transistors, namely the common-source and the common-drain amplifiers. The performance of junctionless devices is evaluated as a function of channel length, nanowire width, doping concentration and bias condition, taking as figures of merit the voltage gain, linearity and, in the case of the common drain amplifier, the input voltage range. The obtained results indicate that these two basic analog blocks can be benefitted by the use of junctionless devices, providing nearly ideal voltage gain when configured as common-drain amplifier, and improvement on voltage gain and linearity with device narrowing in the case of the common-source amplifier. (AU)