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(Reference retrieved automatically from Web of Science through information on FAPESP grant and its corresponding number as mentioned in the publication by the authors.)

Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors

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Author(s):
Trevisoli, Renan [1] ; Doria, Rodrigo Trevisoli [2] ; Barraud, Sylvain [3] ; Pavanello, Marcelo Antonio [2]
Total Authors: 4
Affiliation:
[1] Univ Fed ABC, CECS, Ave Estados 5001, BR-09210580 Santo Andre - Brazil
[2] Ctr Univ FEI, Dept Elect Engn, Av Humberto de Alencar Castelo Branco 3972, BR-09850901 Sao Bernardo Do Campo - Brazil
[3] Univ Grenoble Alpes, CEA, LETI, Minatec Campus, F-38054 Grenoble - France
Total Affiliations: 3
Document type: Journal article
Source: MICROELECTRONIC ENGINEERING; v. 215, JUL 15 2019.
Web of Science Citations: 0
Abstract

The aim of this work is to propose a semi-analytical model for the low frequency noise caused by interface traps in Triple-Gate Junctionless Nanowire Transistors. The proposed model is based on a drain current model, which includes short channel effects influence. The surface potential and the occupied trap density equations are solved self consistently to obtain the traps influence in the static drain current, which is used to determine the trap related noise. In this work, the low frequency noise of traps in discrete levels is analyzed. The model has been validated with 3D simulations considering different devices characteristics, biases and trap levels. Experimental results have also been used to demonstrate the model suitability. (AU)

FAPESP's process: 14/18041-8 - Electrical characterization and modeling of advanced electronic devices
Grantee:Renan Trevisoli Doria
Support type: Scholarships in Brazil - Post-Doctorate