Electrical characterization of vertically stacked p-FET SOI nanowires

This work presents the performance and transport characteristics of vertically stacked p-type MOSFET SOI nanowires (NWs) with inner spacers and epitaxial growth of SiGe raised source/drain. The conventional procedure to extract the effective oxide thickness (EOT) and Shift and Ratio Method (S\&R) have been adapted and validated through tridimensional numerical simulations. Electrical characterization is performed for NWs with {[}1 1 0]- and {[}1 0 0]-oriented channels, as a function of both fin width (W-FIN) and channel length (L). Results show a good electrostatic control and reduced short channel effects (SCE) down to 15 nm gate length, for both orientations. Effective mobility is found around two times higher for {[}1 1 0]-in comparison to {[}1 00]-oriented NWs due to higher holes mobility contribution in (1 1 0) plan. Improvements obtained on I-ON/I-O(FF) by reducing W-FIN are mainly due to subthreshold slope decrease, once small and none mobility increase is obtained for {[}1 1 0]- and {[}1 0 0]-oriented NWs, respectively. (AU)