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(Reference retrieved automatically from Web of Science through information on FAPESP grant and its corresponding number as mentioned in the publication by the authors.)

Drain current model for short-channel triple gate junctionless nanowire transistors

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Paz, B. C. ; Casse, M. ; Barraud, S. ; Reimbold, G. ; Faynot, O. ; Avila-Herrera, F. ; Cerdeira, A. ; Pavanello, M. A.
Total Authors: 8
Document type: Journal article
Source: MICROELECTRONICS RELIABILITY; v. 63, p. 1-10, AUG 2016.
Web of Science Citations: 4

This work proposes a numerical charge-based new model to describe the drain current for triple gate junctionless nanowire transistors (3G JNT). The drain current is obtained through a numerical integration of a single expression that physically describes the junctionless charge density in both accumulation and depletion regimes of operation, leading to a continuous model in all operational regions. The triple gate structure is modeled from an evolution of a previous model designed for double gate junctionless nanowire transistors (2G JNT). Improvements concerning the capacitance coupling, the internal potential changing while reducing the fin height in nanowire transistors and higher immunity to short-channel effects (SCE) are considered. The model validation is performed through both tridimensional numerical simulation and experimental measurements for long and short-channel devices. Through simulated results, it is verified the agreement of the modeled curves for junctionless transistors with different values of fin height. Comparison between the proposed model and experimental data is performed for 3G JNT advanced structures with channel length down to 15 nm and fin height of 8 nm. Results for 3G JNTS with different values of doping concentration and channel width are also displayed showing a good agreement as well. Moreover, 3G JNT performance is also analyzed and compared in the studied structures by extracting the threshold voltage (V-TH), subthreshold slope (S), DIBL and model parameters. (C) 2016 Elsevier Ltd. All rights reserved. (AU)

FAPESP's process: 14/13816-1 - Modeling, electrical characterization and electrical parameter extraction of junctionless MOS transistors
Grantee:Bruna Cardoso Paz
Support Opportunities: Scholarships abroad - Research Internship - Master's degree
FAPESP's process: 12/24377-3 - Modeling of Junctionless Nanowire MOS Transistors with Double and Triple Gate
Grantee:Bruna Cardoso Paz
Support Opportunities: Scholarships in Brazil - Master