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(Reference retrieved automatically from Web of Science through information on FAPESP grant and its corresponding number as mentioned in the publication by the authors.)

Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire Transistors

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Trevisoli, Renan [1] ; Doria, Rodrigo Trevisoli [1] ; de Souza, Michelly [1] ; Pavanello, Marcelo Antonio [1]
Total Authors: 4
[1] Ctr Univ FEI, Dept Elect Engn, BR-09850901 Sao Bernardo Do Campo - Brazil
Total Affiliations: 1
Document type: Journal article
Source: MICROELECTRONIC ENGINEERING; v. 147, p. 23-26, NOV 1 2015.
Web of Science Citations: 3

This work proposes a method for extracting the energetic distribution of the interface trap density at the gate dielectric in Junctionless silicon Nanowire Transistors. The proposed method uses the subthreshold slope extraction combined with the substrate bias in order to induce a variation in the channel potential, such that the interface trap density can be extracted for a significant energy range. Three-dimensional TCAD numerical simulations have been performed to analyze the accuracy of the proposed method considering different concentrations and trap density profiles (uniform and exponential). The influence of the device width variation on the trap energy determination has been analyzed, showing that only for positive substrate biases the energy might be affected. The method precision was also analyzed, showing that the trap density extraction is only effectively affected for low Nit values, which do not influence significantly the device performance. Finally, the method has been applied to experimental transistors with high-x and silicon dioxide gate dielectrics showing consistent results. (C) 2015 Elsevier B.V. All rights reserved. (AU)

FAPESP's process: 14/18041-8 - Electrical characterization and modeling of advanced electronic devices
Grantee:Renan Trevisoli Doria
Support type: Scholarships in Brazil - Post-Doctorate