Advanced search
Start date
(Reference retrieved automatically from Web of Science through information on FAPESP grant and its corresponding number as mentioned in the publication by the authors.)

On the Performance Degradation of Poly(3-Hexylthiophene) Field-Effect Transistors

Full text
Cavallari, Marco R. [1] ; Zanchin, Vinicius R. [2] ; Valle, Marcio A. [1] ; Izquierdo, Jose. E. [3] ; Rodriguez, Eduardo M. [4] ; Rodriguez, Estrella F. G. [4] ; Pereira-da-Silva, Marcelo A. [5] ; Fonseca, Fernando J. [1]
Total Authors: 8
[1] Univ Sao Paulo, Escola Politecn, Dept Engn Sistemas Eletron, BR-05424970 Sao Paulo, SP - Brazil
[2] Univ Sao Paulo EPUSP, Polytech Sch, BR-05508010 Sao Paulo, SP - Brazil
[3] Inst Super Politecn Jose Antonio Echeverria, Ctr Invest Microelect, Havana 10800 - Cuba
[4] Inst Super Politecn Jose Antonio Echeverria, Havana 10800 - Cuba
[5] Univ Sao Paulo, Inst Fis Sao Carlos, BR-13566590 Sao Carlos, SP - Brazil
Total Affiliations: 5
Document type: Journal article
Web of Science Citations: 2

Polymeric transistor degradation was investigated on bottomand top gate structures. Shelf-lifetime studies in both kinds of devices demonstrate an accelerated increase in effective charge carrier mobility, threshold voltage, and off current in modulus when poly(3-hexylthiophene) (P3HT) is exposed to atmospheric gases. Although P3HT is underneath PMMA dielectric and gold gate electrode films, electrical parameters degradation can be only delayed by 100 h. Therefore, only glass encapsulation of the active area is capable of effectively preventing current modulation decrease after exposure to atmospheric gases. Differently from their bottom-gate counterparts, capped top-gate TFTs clearly present negative threshold voltage and positive hysteresis. An interface with reduced deep traps concentration and electrical characterization influence on shallow traps filling are believed to play a significant role in these top-gate P3HT/PMMA transistors under operating conditions. Alternating gate voltage stress along 3000 cycles provides evidence of electrical sweep as a cause of performance degradation. Similarly, dc gate bias stress monitored for 127 min can impair current modulation and shifts threshold voltage depending on its sign. Finally, reversibility of both kinds of stress points that shallow traps are the major problem in these capped devices. (AU)

FAPESP's process: 08/57706-4 - National Institute of Science and Technology on Organic Electronics (INEO)
Grantee:Roberto Mendonça Faria
Support Opportunities: Research Projects - Thematic Grants
FAPESP's process: 13/19420-0 - Gas sensors from organic thin-film transistors
Grantee:Marco Roberto Cavallari
Support Opportunities: Scholarships in Brazil - Post-Doctoral
FAPESP's process: 09/05589-7 - Study and develoment of organic LEDs, solar cells, thin-film transistors and sensors based on semiconductor polymers
Grantee:Adnei Melges de Andrade
Support Opportunities: Regular Research Grants