CV Lattes
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Fundação Educacional Inaciana Padre Sabóia de Medeiros (FEI). Centro Universitário da FEI (UNIFEI). Campus de São Bernardo do Campo (Institutional affiliation from the last research proposal) Birthplace: Brazil
graduate at Engenharia Elétrica from Centro Universitário da Fei (2002), master's at Engenharia Elétrica from Escola Politécnica da Universidade de São Paulo (2005) and ph.d. at Engenharia Elétrica from Escola Politécnica da Universidade de São Paulo (2008). Has experience in Electric Engineering, focusing on Materials and Components Semiconductors, acting on the following subjects: graded-channel soi mosfet, analog applications, soi mosfet, low temperature and analytical continous model. (Source: Lattes Curriculum)
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(Only some records are available in English at this moment)
The constant miniaturization of MOS transistors has hindered the use of traditional technologies in Si substrates, due to the occurrence of short channel effects, which degrade the electrical characteristics of the transistors. The manufacturing technology of integrated circuits (ICs) in SOI wafers has been constituted as an important alternative to conventional CMOS technology, in the pr…
Currently, most electronic circuits use field effect transistors built according to Metal-Oxide-Semiconductor (MOSFET) technology. Scaling semiconductor devices consists of reducing the dimensions of MOS transistors and interconnections in integrated circuits (ICs), allowing for higher density of integration, higher speed and lower power consumption. From an economic point of view, the re…
The Silicon-On-Insulator technology (SOI) has become a real alternative for the Complementary Metal-Oxide-Semiconductor technology (CMOS) implementation to conventional integrated circuits in a very large scale integration in both analog and digital applications. The SOI transistors have a series of advantages over the conventional MOS technology. However, these devices have reduced break…
Silicon-On-Insulator technology constitutes an important alternative to sustain the continuous downscaling of standard CMOS technology. Nowadays, several studies can be found in the literature, regarding the operation of digital circuits with SOI transistors. However, few works report the potential of this technology for high performance analog circuits and devices. Despite of these advan…
(Only some records are available in English at this moment)
| 13 / 12 | Completed research grants |
| 1 / 1 | Ongoing scholarships in Brazil |
| 5 / 4 | Completed scholarships in Brazil |
| 19 / 17 | All research grants and scholarships |
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