Eduardo Marques

• Abstract

  Emerging architectures are both multi-core and heterogeneous offering power and computational efficiency orders of magnitude beyond traditional high-performance systems. Yet, this heterogeneity exacerbates the complexity of the development of applications codes. To address these issues, we will explore the use of a Domain-Specific Language (DSL), for high-level application composition, co…

  Framework for mapping and performance tuning of a weather prediction application on high performance heterogeneous computing systems, AV.EXT

• Abstract

  The use of reconfigurable computing architectures are increasingly important, manifesting itself in a variety of systems, from the computing systems up to high performance embedded systems. The dominant technology for implementation of reconfigurable architectures have been provided by FPGAs1, devices that are based on a matrix of cells surrounded with logical drives resource interconnect…

  Techniques for compiling software into FPGAs, AV.EXT

• Abstract

  High-Performance Computing (HPC) is at the core of many scientific and engineering challenges with tremendous impact in our modern-day life needs. Understanding the causes and predicting and potential impacts of climate change in our natural resources, agricultural productions; improving the efficiency of combustion or developing real-time strategies for physical resource allocation in th…

  Custom heterogeneous hardware acceleration for high-performance computing applications, AV.EXT

(Only some records are available in English at this moment)

• Abstract

  Several critical human activities depend on the weather forecasting. Some of them are transportation, health, work, safety, and agriculture. Such activities require computational solutions for weather forecasting through numerical models. These numerical models must be accurate and allow the computers to process them quickly. In this project we continue our master's research, where we int…

  Mapping and evaluation of ordinary differential equations on heterogeneous architectures, BP.DR

• Abstract

  This research project proposes to develop an open-source processor based on Altera's Nios II processor. The processor will be developed will allow customization of instructions, number of registers, inclusion of components that enable a detailed study of the cache, among other features. Moreover, as the processor will be based on the Nios II architecture, it will be integrated into the Qs…

  Design of an open-source processor in Bluespec Based on Soft-core processor from Altera Nios II, BP.MS
• Combining data and computation transformations for Fine-grain reconfigurable architectures, BP.DR

(Only some records are available in English at this moment)

• Abstract

  Many engineering problems that rely on physical laws and relations can be modelled in the form of differential equations. Differential Equations, in general, are either ODEs or PDEs regarding the number of variables. In this thesis work, we are particularly interested in the acceleration of a chemical reaction simulation that relies on a system of stiff ODEs targeting heterogeneous comput…

  Mapping and evaluation of parallel solution for stiff Ordinary differential equations on heterogeneous architectures based on FPGAs, BE.EP.DR

• Abstract

  This research project proposes to develop an open-source processor based on Altera's Nios II processor. The processor will be developed will allow customization of instructions, number of registers, inclusion of components that enable a detailed study of the cache, among other features. Moreover, as the processor will be based on the Nios II architecture, it will be integrated into the Qs…

  Design of an open-source processor in Bluespec based on Soft-core processor from Altera Nios II, BE.EP.MS

• Abstract

  The project entitled Combining Transformations and Computation Data for Reconfigurable Architectures for Fine Grain aims to research and develop techniques to generate optimized code, considering issues like memory mapping and memory access for reconfigurable architectures, since the latency treading and writing data has been a bottleneck for high performance applications. These technique…

  Combining data and computation transformations for Fine-grain reconfigurable architectures, BE.EP.DR