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Melhorando o codesign hardware/software em memória transacional: uma abordagem baseada em fases e eliminação de instrumentação em excesso

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João Paulo Labegalini de Carvalho
Total Authors: 1
Document type: Doctoral Thesis
Press: Campinas, SP.
Institution: Universidade Estadual de Campinas (UNICAMP). Instituto de Computação
Defense date:
Examining board members:
Guido Costa Souza de Araújo; Márcio Bastos Castro; Alexandro José Baldassin; Marcio Machado Pereira; João Pedro Faria Mendonça Barreto
Advisor: Guido Costa Souza de Araújo

The time when computers were considered just another luxury commodity to have at home or an expensive tool to crunch numbers are long gone. Nowadays, computer science and engineering are at the core of recent advances in many research fields. However, the ever-increasing demand for performance still imposes a challenge to both computer scientists and industry. For decades, the microprocessor industry successfully provided a steady performance increase with each new processor release, leveraged by Moore¿s Law continuous improvement of semiconductor technology. As power density boundaries in semiconductor technology have been reached, the shift from single-core to multicore processing has become the most relevant performance improvement tool in modern computer design. Despite the great potential of multicore machines to meet today¿s demands, their adoption is still modest mainly due to the challenging aspect of concurrent programming. Most concurrent programming models available require programmers to explicitly write their code in a way that all cores are used. Yet the task of synchronizing multiple concurrent accesses to shared resources has proven to be error-prone and far from trivial. In this direction, the Transactional Memory (TM) programming model provides a simple and transparent abstraction to express what needs to be synchronized, with- out requiring the programmer to write synchronization code. TM has the potential to greatly simplify the exploitation of the parallelism available on multicore architectures while simplifying the programmers¿ task. Nonetheless, TM usage and adoption is mostly restricted to research applications, although a large body of research shows the benefits and great performance results that software, hardware and hybrid transactional systems enable. In fact, recently leading researchers in the area backed-off from presenting a re- vised technical specification for standardizing TM in C/C++, after many failed attempts, mainly due to the lack of usage experience. Moreover, although conventional hybrid TM systems allow different transactions to operate in hardware and software, simultaneously, such systems were proven to be inherently limited. Phase-based transactional systems (PhasedTM) are another class of hybrid TMs that execute transactions in non-overlaped phases but, prior to the work described in this manuscript, they were considered as an inferior hybrid variant. In this direction, this thesis makes two contributions to the field of TM. First, it makes a solid case in favor of phase-based transactional memory. And second, it shows how extended compiler support for TM can be used to automatically generate high-performance transactional code. More specifically, this work builds a case for phase-based transactional systems, which were, so far, regarded as inferior variations of conventional hybrid transactional systems. In addition, it proposes a novel annotation mechanism (TMElide) to selectively eliminate unnecessary transactional memory barriers from compiler generated code. This thesis presents the TMElide annotation which extends the C/C++ language type system and how trasactional memory support was incorporated into the Clang/LLVM compiler framework (AU)

FAPESP's process: 16/15337-9 - Distributed Transactional Memories and Efficient Data Distribution Models to Speed-up Irregular Data Structure Intensive Applications
Grantee:João Paulo Labegalini de Carvalho
Support Opportunities: Scholarships in Brazil - Doctorate