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FPGA-BASED HARDWARE ACCELERATOR FOR 5G NETWORK STRUCTURE USING UFMC SIGNAL PRE-CODING TECHNIQUE WITH OPENCL PROGRAMMING LANGUAGE

Grant number: 23/04992-0
Support Opportunities:Scholarships in Brazil - Scientific Initiation
Effective date (Start): July 01, 2023
Effective date (End): June 30, 2024
Field of knowledge:Engineering - Electrical Engineering - Telecommunications
Principal Investigator:Rangel Arthur
Grantee:Gabriel Pedro Paião
Host Institution: Faculdade de Tecnologia (FT). Universidade Estadual de Campinas (UNICAMP). Limeira , SP, Brazil

Abstract

This research project aims at the study and development of an FPGA-based hardware accelerator for the Radio Access Network structure (RAN) of 5G that uses the Open Computing Language (OpenCL) programming language and a pre-coding technique of the Universal Filtered Multi-Carrier (UFMC) signal.The UFMC transmission and reception system will carry out the procedures of mapping, pre-coding, manipulation and later, at the receiver, it will do the inverse process, when the signal is received and sent to the radio equipment to reach the end user. These functions will be divided between the computer and the FPGA hardware, so that the latter works as an accelerator and offloads the processing that would initially be concentrated only on the computer. This work will be done initially through simulation and later by implementation on the FPGA board.The pre-coding technique to be used is to insert a code based on Square Root Raised Cosine (SRC) in the original signal. With its development, an attempt is made to reduce the Peak to Average Power Ratio (PAPR) of the generated waveform and the Bit Error Rate (BER), which are very important parameters to measure the integrity of a telecommunication signal. For analysis of results, it is intended to compare the implementation made in FPGA with the traditional model, without the accelerator device.

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