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Optimizing the Performance of Persistent Memory using Hardware Transactions

Grant number: 23/04971-2
Support Opportunities:Scholarships in Brazil - Post-Doctoral
Effective date (Start): May 01, 2023
Effective date (End): April 30, 2025
Field of knowledge:Physical Sciences and Mathematics - Computer Science - Computer Systems
Principal Investigator:Alexandro José Baldassin
Grantee:Bruno Chinelato Honorio
Host Institution: Instituto de Geociências e Ciências Exatas (IGCE). Universidade Estadual Paulista (UNESP). Campus de Rio Claro. Rio Claro , SP, Brazil
Associated research grant:18/15519-5 - Performance optimizations for multicore architectures, AP.JP2


Non-Volatile Memory (NVM) became commercially available in 2018 with Intel's Optane DC Persistent Memory. NVM allows building data structures that retain their contents to provide fast restart. One major issue is that processor caches are volatile andprogram data which reside in these caches are lost during power failure. In addition, the underlying hardware can evict caches out of order independent from the program order unless explicitly specified by the programmer. Both of these conditions can corruptprogram data in NVM leading to a state that is not correct after restart from a power failure. Transactional Memory (TM) has been a popular programming model for implementing durable data management, in particular with Software Transactional Memory (STM) implementations. Hardware implementations of TM are more desirable due to its better overall performance than STM implementations. This work aims to combine hardware transactional memory with Non-volatile memory to create persistent data structures.

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