STUDY OF THE THERMAL PROPERTIES OF NANOWIRE AND NANOSHEET MOS TRANSISTORS AT CRYOGENIC TEMPERATURES

Abstract

The semiconductor industry owes much of its success to the ability to continually shrink the size of the transistors that make up integrated circuits (ICs). This decrease allows an increase in the number of transistors integrated into a single IC. It also makes it possible to reduce the power consumed, memories with larger storage capacity, and integration of new functionalities into the IC. The constant miniaturization of MOS transistors made the use of traditional MOS technologies, using monocrystalline Si substrates, impractical due to the occurrence of short-channel effects. Undesirably, such effects move the MOS transistor away from its ideal electrical characteristics, promoting an increase in the leakage current, and a reduction in the threshold voltage and subthreshold slope, among other problems. To minimize the short channel effects, three-dimensional MOS transistors with multiple gates, such as FinFETs, started to be used, since they significantly improve the electrostatic control of the charges in the channel region. Recently developed, Si nanowire or nanosheet MOS transistors have shown promising results for the evolution of FinFETs. These structures have a cross-section of a few nanometers (generally 10 to 20 nanometers), enabling excellent electrostatic control in MOS transistors with channel lengths of less than 14 nanometers. These advanced structures have been successfully implemented in silicon-on-insulator (SOI)-type substrates.Among the applications with the potential to use CMOS technology with technological nodes of greater complexity is Quantum Computing. The fundamental cell of quantum computers, the Qubit, is only operational at extremely cryogenic temperatures, in the thousandths of a Kelvin range. Furthermore, Qubits require integration with control and error correction systems, which are implemented in CMOS technology. For this integration to occur, several works have shown that the use of circuits built in CMOS technology operating at temperatures between 77 K to 4 K, instead of at room temperature, offers a lower incidence of noise and, consequently, alleviates the need for error correction.The operation of MOS transistors at highly cryogenic temperatures presents some improvements in the electrical characteristics of the devices, such as reduced subthreshold slope, greater carrier mobility, and greater electrical current. However, the current flow causes the Joule Effect, increasing the transistor's temperature, in opposition to the improvements mentioned. This effect is known as self-heating and is especially problematic for transistors larger than Si. The knowledge of the thermal properties of MOS transistors made of nanowires and Si nanosheets as a function of the ambient temperature, especially their ability to operate at cryogenic temperatures, is of fundamental importance for their adoption in circuits such as those used in quantum computing.This research project aims to evaluate, using three-dimensional numerical simulations and experimental measurements, the electrical properties of state-of-the-art SOI MOS transistors of nanowires and Si nanosheets operating from room temperature to the cryogenic range, suitable for interface circuits with Qubits. . This exhibition will allow obtaining relevant data for I) the evolution of these transistors for operation at cryogenic temperatures; II) development of compact models for the simulation of electronic circuits in CMOS technology using these state-of-the-art structures, III) adaptation of numerical simulation models to carry out simulations at cryogenic temperatures, allowing the observation of relevant internal variables.