Over the past decades, MOS transistors have been the most applied electronic components in integrated circuits, so that the development of the microelectronics industry is conditioned to their evolution. By reducing the dimensions of MOS transistors, it is possible to increase the number of devices per chip, increasing the processing capacity. However, the scaling of the transistors dimensions to extreme values, results in the reduction of the channel charge control by the gate, causing the so-called short channel effects that degrade their electrical characteristics. Therefore, several technologies have been developed to allow the scaling of MOS transistors in advanced technological nodes (sub-20nm), such as multi-gate transistors, also called 3D, which are less susceptible to short-channel effects. In order to further improve the control of charges in the channel region, 3D transistors can be fabricated using Silicon-on-Insulator (SOI) technology, where the wafer active region is separated from the substrate by an insulating layer. The presence of this layer improves the capacitive coupling in the channel region and allows the fabrication of devices that work in partial depletion/accumulation mode, such as junctionless transistors, in which the doping of the channel region is high and constant from source to drain. These devices were proposed for state-of-the-art technologies (sub-16nm), where the formation of source/drain junctions is a critical step in the manufacturing process. Although junctionless transistors are extremely promising, the formation of their conduction channel has a strong dependence on the gate biasing condition and on physical characteristics of the devices such as dimensions and doping concentration. Thus, these devices are subject to significant variability in their electrical characteristics. Recently, some simulation and experimental works have been developed aiming to determine the variability of junctionless transistors. However, few of them have dealt with P-type channel devices. Therefore, the current work aims at the experimental electrical characterization and simulation of P-type channel junctionless transistors and extraction of their main electrical parameters, such as threshold voltage and subthreshold slope. From the results, it will be possible to verify if the variability of transistors without P-channel junctions present behavior similar to that of nMOS transistors, despite the lower mobility of holes in relation to electrons, as well as particularities in the process of implantation of dopants.
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