Simulation and electrical characterization of nanowire MOS transistors at high temperatures

Abstract

The semiconductor industry owes much of its success to the ability to continually shrink the size of the devices (basically transistors) that make up integrated circuits (chips). This decrease in the size of the devices allows an increase in the number of transistors integrated on a single chip. It also makes it possible to reduce the power consumed, manufacture larger memories and integrate new features into the chip.The constant miniaturization of MOS transistors, reaching tens of nanometers in channel length, has made it difficult to use traditional MOS technologies, manufactured in monocrystalline Si substrates, due to the presence of short channel effects. In an undesirable way, such effects take the MOS transistor away from its ideal electrical characteristics, promoting an increase in the cut-off current, reduction of the threshold voltage, and sub-threshold inclination, among other problems. Recently, as a way to minimize the effects of miniaturization, MOS transistors with multiple ports, such as FinFETs, started to be used, since they significantly improve the electrostatic charge control in the channel region, reducing the incidence of short channel effects.Recently developed, MOS transistor nanowires have shown promising results for the evolution of FinFETs. These structures have a cross-section of a few nanometers (usually 10 to 20 nanometers), allowing excellent electrostatic control in MOS transistors with channel lengths less than 14 nanometers.The operation of electronic devices at high temperatures is associated with a series of applications, in which the electronic system is subjected to temperatures above the ambient and which can exceed 600 K, depending on the branch of application. The operation of transistors in systems commonly used in consumer electronics, such as smartphones, laptops, or televisions, rarely occurs at room temperature and easily reaches the 340K range.When subjected to higher temperatures than the ambient temperature, electronic devices suffer a degradation of their electrical properties, which worsens as the temperature of the environment is higher. In the case of MOS transistors, there is an increase in the leakage current of the PN junctions, a reduction in the threshold voltage, an increase in the sub-threshold inclination, and a reduction in the mobility of the load carriers, among other effects.Thus, the evaluation of changes in the electrical characteristics of the MOS transistor nanowires as the temperature increases, it is important to understand the associated physical effects, determine the limits of use of this technology and include them in compact models used in the design of electronic circuits tolerant to temperature rise.In this context, this Scientific Initiation research project aims at the three-dimensional numerical simulation and the carrying out of electrical measurements of MOS transistor nanowires, in the temperature range between at least 300 K and 573 K. With the three-dimensional numerical simulations and the experimental measurements performed, its main electrical parameters will be extracted. The results obtained from the three-dimensional numerical simulations will be compared to the experimental results, deepening the knowledge about the electrical properties of MOS transistors nanowires, when subjected to variable temperature conditions. This comparison will also allow an appropriate adjustment of the three-dimensional simulation structures in this temperature range, which will serve for the development of other associated researches, which depends on a good fidelity between the simulated structure and the experimental results. MOS transistor nanowires will be used for electrical measurements manufactured in CEA-Leti, France.