Advanced search
Start date
Betweenand

Study of FinFET transistor behavior and its application in logic gates

Grant number: 19/13558-6
Support Opportunities:Scholarships in Brazil - Scientific Initiation
Effective date (Start): September 01, 2019
Effective date (End): July 31, 2021
Field of knowledge:Engineering - Electrical Engineering - Electrical, Magnetic and Electronic Measurements, Instrumentation
Principal Investigator:Paula Ghedini Der Agopian
Grantee:Gustavo Vinicius de Araujo
Host Institution: Universidade Estadual Paulista (UNESP). Campus Experimental São João da Boa Vista. São João da Boa Vista , SP, Brazil

Abstract

The SOI (Silicon-On-Insulator) technology that has been used since the early 2000s to minimize short-channel effects to very small (nanometric) dimensions has also not been enough when it we think in planar transistors. Thus a new proposal for multi-gate transistors, also known as FinFET transistors, appears as an alternative to planar ones due to its better electrostatic coupling between gate and channel, resulting in better control of channel charges and consequently greater immunity to short-channel effects .In this project of scientific initiation will be realized the theoretical and experimental study of the FinFETs transistors to apply them in basic logic gates.

News published in Agência FAPESP Newsletter about the scholarship:
More itemsLess items
Articles published in other media outlets ( ):
More itemsLess items
VEICULO: TITULO (DATA)
VEICULO: TITULO (DATA)

Please report errors in scientific publications list using this form.