Efficient implementation of blind equalization algorithms in FPGA

Abstract

This scientific initiation research project aims to investigate the performance of blind equalization adaptive algorithms implemented in a dedicated hardware. Special attention will be given to the implementation of a normalized version of the constant modulus algorithm (CMA). Although the stability of this algorithm has been theoretically demonstrated and verified with numerical simulations in the literature, its behavior has not yet been verified experimentally in practice. We envisage to use the Xilinx ZYNQ-7000 platform with the FPGA XC7Z020-CLG484, which has been designated for its memory and processing capabilities adequate for the implementation. The hardware implementation will essentially evaluate the functionality of the algorithms operating in real time. The results will be analyzed for the purpose of evaluating convergence speed, computational complexity, and numerical stability of the blind equalization algorithms in situations close to practical applications. (AU)