Evaluation and Modeling of Charge Transport in Nanometer MOSFETs for CMOS Circuit Design

Abstract

Multiple gate MOS transistors are a promising alternative to solve the problems arising from the continued reduction of the device dimensions, due to the improvements in the performance of MOS devices with extremely submicron dimensions (deep-submicrometer), with channel lengths smaller than 14 nm, because of the excellent control of channel charges.The double or triple gate transistors, such as FinFETs or with surrounding channel, are examples of structures that have been considered by the scientific community. Recently, a new transistor structure with multiple gates was proposed, the MOS transistor without junctions (junctionless). In this transistor channel, source and drain regions are made from the same type of dopant, avoiding the PN junctions. Juntionless devices demonstrated improvements to be applied in both digital and analog applications in comparison to standard MOSFETs with multiple gates and similar dimensions (with junctions). In addition to the absence of juctions, the charge transport in these transistors occurs in a completely different way than occurs in traditional MOS transistors. The junctionless devices have carriers transport based on accumulation regime in the channel region, while transistors with junctions are based on inversion phenomenon.Because of this change in physics governing the transport of charges in junctionless transistors, few studies can be found in the current literature regarding the carrier transport properties in these advanced structures. However, these few publications still present preliminary findings on the subject and they all perform technical adptions on methods applied to traditional transistors as a way to get information about the charge transportation of transistors without junctions. Detailed knowledge and subsequent modeling of physical phenomena governing the charge transport in junctionless transistors is critical because it directly impacts the electrical current and thus the performance of these devices in electrical circuits.In this research project will be carried out a comparative study of charge transportation in traditional transistors and junctionless, both structures with multiple doors and nanometric dimensions. It is expected to get a new model for the mobility of carriers in the channel region of the junctionless MOS transistors, which consider the peculiarities of operation of these structures to be included in electrical circuit simulators.