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Distributed Transactional Memories and Efficient Data Distribution Models to Speed-up Irregular Data Structure Intensive Applications

Grant number: 16/15337-9
Support Opportunities:Scholarships in Brazil - Doctorate
Effective date (Start): August 01, 2016
Effective date (End): July 31, 2020
Field of knowledge:Physical Sciences and Mathematics - Computer Science - Computer Systems
Principal Investigator:Guido Costa Souza de Araújo
Grantee:João Paulo Labegalini de Carvalho
Host Institution: Instituto de Computação (IC). Universidade Estadual de Campinas (UNICAMP). Campinas , SP, Brazil
Associated research grant:13/08293-7 - CCES - Center for Computational Engineering and Sciences, AP.CEPID
Associated scholarship(s):19/01110-0 - Novel code analysis to identify constructs suitable for hardware primitives, BE.EP.DR


The rapid and significant growth in computing power of both commodity and high-performance machines has not been accompanied by a similar gain in productivity, of average programmers, on writing efficient code, capable of exploiting the ever increasing parallelism and heterogeneity of hardware. A recent shift towards IaaS (Infrastructure as a Service) has enabled programmers to use HPC (High-Performance Computing), also, as a service. However, in order to benefit from such environments, programmers are still obliged to either rethink their problem in new languages or functional programming models or take full control over data and communication. In this context, this project will study how recent hardware features and novel programming abstractions can be coupled to enhance existing, or to create language extensions and help HPC developers to write efficient, easier to maintain and scalable code.

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Scientific publications
(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)
DE CARVALHO, JOAO P. L.; ARAUJO, GUIDO; BALDASSIN, ALEXANDRO. The Case for Phase-Based Transactional Memory. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, v. 30, n. 2, p. 459-472, . (16/15337-9)
Academic Publications
(References retrieved automatically from State of São Paulo Research Institutions)
CARVALHO, João Paulo Labegalini de. Melhorando o codesign hardware/software em memória transacional: uma abordagem baseada em fases e eliminação de instrumentação em excesso. 2020. Doctoral Thesis - Universidade Estadual de Campinas (UNICAMP). Instituto de Computação Campinas, SP.

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