Scholarship 16/15337-9 - Paralelismo, Computação distribuída - BV FAPESP
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Distributed Transactional Memories and Efficient Data Distribution Models to Speed-up Irregular Data Structure Intensive Applications

Grant number: 16/15337-9
Support Opportunities:Scholarships in Brazil - Doctorate
Start date until: August 01, 2016
End date until: July 31, 2020
Field of knowledge:Physical Sciences and Mathematics - Computer Science - Computer Systems
Principal Investigator:Guido Costa Souza de Araújo
Grantee:João Paulo Labegalini de Carvalho
Host Institution: Instituto de Computação (IC). Universidade Estadual de Campinas (UNICAMP). Campinas , SP, Brazil
Associated research grant:13/08293-7 - CCES - Center for Computational Engineering and Sciences, AP.CEPID
Associated scholarship(s):19/01110-0 - Novel code analysis to identify constructs suitable for hardware primitives, BE.EP.DR

Abstract

The rapid and significant growth in computing power of both commodity and high-performance machines has not been accompanied by a similar gain in productivity, of average programmers, on writing efficient code, capable of exploiting the ever increasing parallelism and heterogeneity of hardware. A recent shift towards IaaS (Infrastructure as a Service) has enabled programmers to use HPC (High-Performance Computing), also, as a service. However, in order to benefit from such environments, programmers are still obliged to either rethink their problem in new languages or functional programming models or take full control over data and communication. In this context, this project will study how recent hardware features and novel programming abstractions can be coupled to enhance existing, or to create language extensions and help HPC developers to write efficient, easier to maintain and scalable code.

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Scientific publications (7)
(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)
BALDASSIN, ALEXANDRO; MURARI, RAFAEL; DE CARVALHO, JOAO P. L.; ARAUJO, GUIDO; CASTRO, DANIEL; BARRETO, JOAO; ROMANO, PAOLO; MALAWSKI, M; RZADCA, K. NV-PhTM: An Efficient Phase-Based Transactional System for Non-volatile Memory. EURO-PAR 2020: PARALLEL PROCESSING, v. 12247, p. 16-pg., . (13/08293-7, 18/15519-5, 19/10471-7, 16/15337-9)
HONORIO, BRUNO CHINELATO; DE CARVALHO, JOAO P. L.; BALDASSIN, ALEXANDRO; BIANCHINI, CD; DESOUZA, PSL; DEBARROS, COF; FERREIRA, RAC. On the Efficiency of Transactional Code Generation: A GCC Case Study. 2018 SYMPOSIUM ON HIGH PERFORMANCE COMPUTING SYSTEMS (WSCAD 2018), v. N/A, p. 7-pg., . (16/12103-7, 16/15337-9)
DE CARVALHO, JOAO P. L.; ARAUJO, GUIDO; BALDASSIN, ALEXANDRO. The Case for Phase-Based Transactional Memory. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, v. 30, n. 2, p. 459-472, . (16/15337-9)
HONORIO, BRUNO CHINELATO; DE CARVALHO, JOAO P. L.; SKAF, MUNIR; ARAUJO, GUIDO; MILFELD, K; DESUPINSKI, BR; KOESTERKE, L; KLINKENBERG, J. Using OpenMP to Detect and Speculate Dynamic DOALL Loops. OPENMP: PORTABLE MULTI-LEVEL PARALLELISM ON MODERN SYSTEMS, v. 12295, p. 16-pg., . (19/04536-9, 13/08293-7, 16/15337-9, 19/01110-0)
DE CARVALHO, JOAO P. L.; HONORIO, BRUNO C.; BALDASSIN, ALEXANDRO; ARAUJO, GUIDO; IEEE. Improving Transactional Code Generation via Variable Annotation and Barrier Elision. 2020 IEEE 34TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM IPDPS 2020, v. N/A, p. 10-pg., . (19/04536-9, 13/08293-7, 16/15337-9, 18/15519-5)
DE CARVALHO, JOAO P. L.; KUZMA, BRAEDY; ARAUJO, GUIDO; ASSOC COMP MACHINERY. Acceleration Opportunities in Linear Algebra Applications via Idiom Recognition. ICPE'20: COMPANION OF THE ACM/SPEC INTERNATIONAL CONFERENCE ON PERFORMANCE ENGINEERING, v. N/A, p. 2-pg., . (13/08293-7, 16/15337-9, 19/01110-0)
MATTOS, LUIS; CESAR, DIVINO; SALAMANCA, JUAN; DE CARVALHO, JOAO P. L.; PEREIRA, MARCIO; ARAUJO, GUIDO; IEEE. DOACROSS Parallelization based on Component Annotation and Loop-carried Probability. 2018 30TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD 2018), v. N/A, p. 4-pg., . (13/08293-7, 16/15337-9, 15/04285-5)
Academic Publications
(References retrieved automatically from State of São Paulo Research Institutions)
CARVALHO, João Paulo Labegalini de. Melhorando o codesign hardware/software em memória transacional: uma abordagem baseada em fases e eliminação de instrumentação em excesso. 2020. Doctoral Thesis - Universidade Estadual de Campinas (UNICAMP). Instituto de Computação Campinas, SP.

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