With the continuous reduction of devices, CMOS technology manufacturing, which currently reached nanometric scales, has been faced with problems such as short channel effects. As an alternative to this technology, industries have replaced conventional CMOS technology for silicon on insulator (SOI) technology and multi-gate structures (MuGFETs). However, for dimensions below 22nm even this technology has reached its limit of escalation.Due to the limit of this scaling, new alternatives have been studied to replace the MOS technology. Among these alternatives, one can cite the tunneling field-effect transistor (TFET) which is a silicon-based device and compatible with MOS technology, but with different operating principle. In these devices the current is composed by the carriers that tunneling between bands, which makes possible the very significantly reduction of the off-state current (IOFF) and also a very steep subthreshold slope (below the theoretical limit - 60mV / dec) at room temperature.This work aims to study these new structures, MuGFETs and TFETs of nanometric dimensions, which have been the alternatives identified by the scientific community as promising for the replacement of conventional MOS devices. In the case of multi-gate transistors, this improvement is due to better control of the charges in the channel and consequently smaller short channel effect, while tunneling transistors are a good alternative due to the fast switching speed and lower power dissipation.
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