Radiation effects on triple-gate tunnel-FETs transistors

Abstract

With the continuous reduction of the devices, the CMOS technology has been faced with problems such as short channel effects. Alternatively, the main industries have replaced the conventional CMOS technology by silicon on insulator (SOI) one. However, for dimensions below 22nm, even this technology has reached the limits of its escalation. Among the most promising alternatives studied by the scientific community to replace the MOS technology, one can cite the tunnel field effect transistor (TFET ), which is a device compatible with MOS technology, but with a different operation principle. In these devices the current is composed by tunneling of carriers among bands, which makes possible a significant reduction in the off-state current (IOFF) and also a subthreshold slope below the theoretical limit (60mV / dec at room temperature) This new device has a great potential for switching speed. This work aims to study the behavior of tunnel-FET transistors when submitted to radiation through a comparative analysis of the performance of these transistors before and after radiation. This study will take place both through experimental measurements, and with the numerical simulation devices (Atlas and / or Sentaurus) for different operating temperatures. (AU)