The Silicon-On-Insulator technology (SOI) has become a real alternative for the Complementary Metal-Oxide-Semiconductor technology (CMOS) implementation to conventional integrated circuits in a very large scale integration in both analog and digital applications. The SOI transistors have a series of advantages over the conventional MOS technology. However, these devices have reduced breakdown voltage due to the floating-body effect which causes the activation of the parasitic bipolar transistor associated with the MOS transistor. In order to minimize the occurrence of parasitic bipolar effects and improve the analog characteristics of SOI transistors, it has been designed a structure named as asymmetric self-cascode of SOI transistors. Several results demonstrate the great potential of this structure at device level and in analog applications.In this PhD work, it will be first studied the analog characteristics of asymmetric self-cascode with several dimensions, implemented with transistors from different technologies, such as planar and junctionless. It will be also performed experimental measurements of the low frequency noise of asymmetric self-cascode, as well as the drain current modeling, with the aim of allowing its use in a circuit simulator such as Eldo. Furthermore, it will be studied the impact of the asymmetric self-cascode in analog blocks, through two-dimensional and three-dimensional numerical simulations and circuits simulations. Finally, it will be designed, fabricated and characterized an operational amplifier implemented with asymmetric self-cascode of SOI transistors.
News published in Agência FAPESP Newsletter about the scholarship: