Code snippets identification for pipeline processing in FPGA accelerators for heterogeneous platforms

Abstract

High performance computing is an increasing field in computer sciences since the computational evolution in the last years has created systems that allow the acquisition of big data sets, opening the gap on how to process these data efficiently. Heterogeneous computing shows promising results dealing with such big sets of data by exploring parallel computations and the processors affinity of the computations. Between heterogeneous platforms, the most common are GPP and GPU working together, which has been explored for quite a few years and has reached a well advanced state of art, resulting in common commercial solutions. The usage of FPGAs is more recent and limited by the development complexity, but with good power efficiency and low latency results. In this project we propose technique to identify pipeline computations on high level sequential codes to be used on FPGAs accelerators creation in a heterogeneous platform, since such computations are efficiently mapped on FPGAs when compared with its implementations on graphic processors or multi-core architectures. (AU)