Advanced electronic devices such as Junctionless Nanowire Transistors (JNTs) have been developed aiming at a larger scaling of the devices in comparison with conventional MOSFETs, due to the better electrostatic control of the channel charges, minimizing the short-channel effects occurrence. Therefore, JNTs provide a better miniaturization of electronic devices.Aiming at the analysis of the device operation in electric circuits, analytical models are necessary. These models must be functional for transistors of different characteristics such as doping concentration and dimensions, operating at different biases and temperatures. The models should also comprise both static and dynamic behaviors. The later is related with the device intrinsic capacitances. However, the dynamic behavior of junctionless devices has barely been explored in the literature, specially the modeling of triple gate JNTs, which are the most important in terms of applications.Therefore, the main objective of this project is to model the dynamic behavior of electronic devices, focusing on the junctionless triple gate transistors. To develop the project, both numerical simulations and electrical characterization are necessary. The static behavior should also be analyzed, since it interferes in the charges distribution and in the capacitances. Other devices such as FinFETs and undoped nanowires may also be analyzed for comparison purposes. (AU)
News published in Agência FAPESP Newsletter about the scholarship:
DORIA, RODRIGO TREVISOLI;
DE SOUZA, MICHELLY;
PAVANELLO, MARCELO ANTONIO.
A New Method for Series Resistance Extraction of Nanometer MOSFETs.
IEEE TRANSACTIONS ON ELECTRON DEVICES,
Web of Science Citations: 4.