Using hardware transactional support to accelerate software transactional memory systems

Abstract

The limited performance gain due to micro-architectural optimizations and the modest increase in clock rate led the microprocessor industry to seek alternatives to single-core processors in order to keep up with the performance demand. The solution found was to build architectures with multiple execution flows (multicore). Nonetheless, the parallel model immediate adoption requires programmers to explicitly code applications in a way that all cores are used. Yet this task has proven to be non-trivial and prone to errors which are difficult to detect. A new concurrent programming model known as transactional memory (TM) brings abstractions that ease the synchronization burdens of parallel coding and enables programmers to better exploit the parallelism of multicore architectures without knowing its details. However, software and hardware implementations of the TM model have proven to be limited when adopted in isolation. Hybridtransactional systems (HyTM) are the proposed solution to these problems, allowing aplications to benefit from multicore machines.As only recently processors with transactional execution support were made commercially available and, as evaluations have been conducted through simulated environments, little is known about how hardware transactional support can be employed as an accelerator to concurrent aplications. In this direction, this Master project will investigate new techniques that use the recently added transactional memory hardware support to speed up software transactional memory systems.