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Using hardware transactional support to accelerate software transactional memory systems

Grant number: 14/00534-8
Support Opportunities:Scholarships in Brazil - Master
Effective date (Start): August 01, 2014
Effective date (End): February 29, 2016
Field of knowledge:Physical Sciences and Mathematics - Computer Science - Computer Systems
Principal Investigator:Alexandro José Baldassin
Grantee:João Paulo Labegalini de Carvalho
Host Institution: Instituto de Geociências e Ciências Exatas (IGCE). Universidade Estadual Paulista (UNESP). Campus de Rio Claro. Rio Claro , SP, Brazil
Associated research grant:11/19373-6 - Understanding and exploiting energy/performance tradeoffs in concurrent algorithms, AP.JP


The limited performance gain due to micro-architectural optimizations and the modest increase in clock rate led the microprocessor industry to seek alternatives to single-core processors in order to keep up with the performance demand. The solution found was to build architectures with multiple execution flows (multicore). Nonetheless, the parallel model immediate adoption requires programmers to explicitly code applications in a way that all cores are used. Yet this task has proven to be non-trivial and prone to errors which are difficult to detect. A new concurrent programming model known as transactional memory (TM) brings abstractions that ease the synchronization burdens of parallel coding and enables programmers to better exploit the parallelism of multicore architectures without knowing its details. However, software and hardware implementations of the TM model have proven to be limited when adopted in isolation. Hybridtransactional systems (HyTM) are the proposed solution to these problems, allowing aplications to benefit from multicore machines.As only recently processors with transactional execution support were made commercially available and, as evaluations have been conducted through simulated environments, little is known about how hardware transactional support can be employed as an accelerator to concurrent aplications. In this direction, this Master project will investigate new techniques that use the recently added transactional memory hardware support to speed up software transactional memory systems.

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Academic Publications
(References retrieved automatically from State of São Paulo Research Institutions)
CARVALHO, João Paulo Labegalini de. PhTM*: an efficient implementation of phased transactions. 2016. Master's Dissertation - Universidade Estadual Paulista (Unesp). Instituto de Geociências e Ciências Exatas. Rio Claro Rio Claro.

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