With the advance in the fabrication of integrated circuits technology, the transistors dimensions have been reduced to nanometric sizes, where problems as the short channel effect and the high dissipated power in the device become critical.In order to minimize the problem regarding the short channel effect emerged the structural alternative of replacing the traditional single-gate MOSFET transistor by a multiple gate transistor, such as the double gate (FinFET), triple gate (3D transistor) and gate all around transistors. In the last case, performance is significantly better if the transistor body has a circular cross section and with a small diameter, also called nanowire.However, to minimize the dissipated power, it is necessary the advent of a technology, whose behavior is as close as possible to the behavior of an ideal switch, i.e. with a subthreshold slope lower than 60mV/dec at room temperature. It is in this context that the tunneling transistors induced by field effect (TFET) appear, and besides their compatibility with the MOS technology, their operating principles are very different. In these devices, the electric current is composed of carriers that tunnel from the source valence band to the channel conduction band, instead of the traditional mechanism of source to drain diffusion/drift, normally found in the MOS transistors. This makes possible that TFET behaves like a switch closer to the ideal.This master thesis aims to study a Tunnel-FET transistor (TFET) manufactured in nanowire structure. This study will consist of a theoretical (numerical simulation) and an experimental part. The digital and analog characteristics of the device and its potential for use in advanced integrated circuits for the next decade will be studied.
News published in Agência FAPESP Newsletter about the scholarship: