Modeling of Junctionless Nanowire MOS Transistors with Double and Triple Gate

Abstract

The continuous scaling of electronic devices has hampered the use of planar MOS transistors in technologies with nanometric dimensions due to the presence of short channel effects. Multiple gate MOS transistors significantly improve the charge control in the channel region, reducing such effects. Therefore these devices have been considered very promising in future technologies.Many multiple gate transistors, such as double or triple gate FinFETs and surrounding channel devices, have earned quite of attention from scientific community due to its great performance in digital application. Other multiple gate structure, recently developed, that has presented promising results is the junctionless MOS transistor, which has source, drain and channel regions made of the same type and concentration of dopants, eliminating PN junctions.In this project, analytical modeling and electrical characterization will be analyzed for nanometric dimensions junctionless MOS transistors. In order to validate the developed analytical model, tridimensional simulations of these devices will be performed. For the model validation through experimental results, it will be used junctionless MOS transistors fabricated at CEA-Leti, in Grenoble, France.