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Modeling of Junctionless Nanowire MOS Transistors with Double and Triple Gate

Grant number: 12/24377-3
Support Opportunities:Scholarships in Brazil - Master
Effective date (Start): May 01, 2013
Effective date (End): April 30, 2015
Field of knowledge:Engineering - Electrical Engineering - Electrical Materials
Principal Investigator:Marcelo Antonio Pavanello
Grantee:Bruna Cardoso Paz
Host Institution: Campus de São Bernardo do Campo. Centro Universitário da FEI (UNIFEI). Fundação Educacional Inaciana Padre Sabóia de Medeiros (FEI). São Bernardo do Campo , SP, Brazil
Associated scholarship(s):14/13816-1 - Modeling, electrical characterization and electrical parameter extraction of junctionless MOS transistors, BE.EP.MS


The continuous scaling of electronic devices has hampered the use of planar MOS transistors in technologies with nanometric dimensions due to the presence of short channel effects. Multiple gate MOS transistors significantly improve the charge control in the channel region, reducing such effects. Therefore these devices have been considered very promising in future technologies.Many multiple gate transistors, such as double or triple gate FinFETs and surrounding channel devices, have earned quite of attention from scientific community due to its great performance in digital application. Other multiple gate structure, recently developed, that has presented promising results is the junctionless MOS transistor, which has source, drain and channel regions made of the same type and concentration of dopants, eliminating PN junctions.In this project, analytical modeling and electrical characterization will be analyzed for nanometric dimensions junctionless MOS transistors. In order to validate the developed analytical model, tridimensional simulations of these devices will be performed. For the model validation through experimental results, it will be used junctionless MOS transistors fabricated at CEA-Leti, in Grenoble, France.

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Scientific publications
(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)
PAZ, B. C.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; FAYNOT, O.; AVILA-HERRERA, F.; CERDEIRA, A.; PAVANELLO, M. A.. Drain current model for short-channel triple gate junctionless nanowire transistors. MICROELECTRONICS RELIABILITY, v. 63, p. 1-10, . (14/13816-1, 12/24377-3)

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