The fabrication technology development of integrated circuit (IC) is responsible for the radical change in informatics and telecommunications. For this development, the transistors that compose the main manufacture technology of ICs in bulk silicon (Bulk-CMOS: Complementary Metal - Oxide - Semiconductor) suffer continuous reduction size, reaching nanometer scales.Among the main problems found for the technological development, there are the short channel effects and the high power dissipation in the integrated circuits. In order to minimize these problems the Silicon-On Insulator CMOS technology (SOI-CMOS) has been used, which allows the fabrication of planar (single gate) and 3D (multiple gate) devices. However for dimension below 16 nm, some new technologies have to be developed.Looking for new solutions to continuing devices integration, the scientific community has studied devices, that are compatible with CMOS technology, but with different operating principles. One of the options is the Tunneling Field Effect Transistor (TFET). In these devices the drain current consists of carriers that tunneling from the valence band to the conduction band rather than the drift/diffusion mechanism usually found in MOS transistors. This allows the TFET behaves as an near-ideal switch by reducing short channel effect and reducing the power dissipated.This work aims to study this new transistor, called the TFET, which recently has shown to be a good option for the conventional MOS transistors replacement. The electrical performance of this device will be studied as a function of its geometries through numerical simulations and experimental measurements. The behavior of TFETs with temperature variation will be also studied.
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