Wear-leveling techniques for PRAM memories

Abstract

The phase-change memories bring new opportunities for the computer industry, is to create non-volatile storage devices with greater durability or is to replace DRAM because its limit of scalability. Although promising, PRAM memories nowadays need mechanisms to reduce wear. At this point wear-leveling techniques allow us to spread the wear evenly by the memory, so that increases the durability of memory as a whole. In spite of there are techniques currently used in some memories, like NAND flash, there is room for innovation and research. In this scenario we propose a technique that attempts to organize a new form the relating informations of virtual and physical addresses, allowing to create temporary bonds between them, so that each new writing in a particular virtual address the data will be located in physical different regions, preventing local wear. (AU)