Acquisition and digital signal processing Board - SPOS2

Abstract

There is a lack of suppliers of high performance digital signal processing boards in the world market. The costs are high and the corresponding technical assistance is insufficient. Therefore, there is a need of developing and producing these boards in Brazil. This is the main task of this request: design and produce a new high performance digital processing board, hereby called SPOS-2. In particular, the new board will have an immediate use in strategic military applications for the defense of the country, as for the border surveillance and air traffic monitoring. Indeed, this is one of the segments of Bradar Indústria S.A., belonging to the Embraer Defesa e Segurança, and proponent of this research project.From 2007 to 2008, with subvention from FINEP (Financiadora de Estudos e Projetos); Bradar developed a high performance digital processing board denominated SPOS-1. The development of the SPOS-1 was crucial for the success of a wide range of products of the company and it is still used in quite all the products. However, due to the quick technological progress in the field of microelectronics and of signal processing, it is achieving obsolescence and can't satisfactorily comply with the requirements of new products and applications. The SPOS-2 will cover these needs, substituting the SPOS-1. For complying with the new requirements the SPOS-2 will be developed using last generation and highest processing power components. It's analog interface will allow the acquisition and transmission of high bandwidth signals, and it's components will carry out advanced processing algorithms. More specifically, one proposes the evaluation of two critical functionalities of the board for the Phase 1 of the project: the power supply and the system clock distribution. The quality of these two functionalities affects directly important tasks of the system, as the effective number of bits of the Analog-to-Digital converters, ADCs, and Digital-to-Analog converters, DACs. The power supply can introduce noise and the clock distribution can cause unexpected delays and jitters. In particular, radar systems must transmit coherently and with phase stability and, for achieving them, clock signal paths must have identical length, the impedance must be well defined and the jitter must be lower than 100 fs (fento-seconds). Concluding the validation of Phase 1, Phase 2 will be the design and construction of the complete board with a last generation FPGA, ADCs, DACs, DDR4 memory, memory cards and test/production environment. (AU)