Virtual reconfigurable architecture for image processing in real time

Abstract

In the present scientific project is intended to continue the work of previous research (FAPESP: 2009/17736-4), which it was implemented an original architecture for image processing in real time. The developed architecture has been implemented in a FPGA, and it has low cost and low energy consumption. Furthermore, it can be reconfigurable through linear and non linear instructions that are automatically generated by software using a genetic programming approach. There are several applications for this system, such as: pattern recognition and filter emulation in real time. The images are supplied by a video camera to the system, and the results can be seen in real time through a video monitor. The architecture can handle binary, gray-level, and color images, too. However, despite all previous contributions, the training process of the architecture demands too time, and it can be improved. Thus, in this work is intended to increase the complexity of this architecture aiming to develop and add a virtual training module directly in the FPGA, in order to reduce processing time for this stage. To achieve this purpose, it will be used a novel approach based on genetic programming, named Cartesian Genetic Programming, that it is intended for hardware evolution. Thus, the genetic parameters as well as the training images will be passed to the system through a computer program, to be developed in Matlab, and the evolutionary process along the evaluation of the chromosomes will be processed in hardware so the training time should be reduced. Therefore, the possibilities for this system are many, and the proposed architecture should be flexible to adapt itself to several problems involving computer vision with hardware performance. Finally, the system can be used as a support tool by image processing specialists. (AU)