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Design, fabrication and characterization of FinFET transistors

Grant number: 08/05792-4
Support Opportunities:Research Projects - Thematic Grants
Duration: March 01, 2009 - August 31, 2013
Field of knowledge:Engineering - Electrical Engineering
Principal Investigator:João Antonio Martino
Grantee:João Antonio Martino
Host Institution: Escola Politécnica (EP). Universidade de São Paulo (USP). São Paulo , SP, Brazil
Pesquisadores principais:
Jose Alexandre Diniz ; Marcelo Antonio Pavanello ; Sebastiao Gomes dos Santos Filho
Associated researchers:Antonio Carlos Seabra ; Mariana Pojar de Melo ; Milene Galeti ; Newton Cesario Frateschi ; Paula Ghedini Der Agopian ; Renato Camargo Giacomini ; Ronaldo Willian Reis ; Simone Camargo Trippe ; Stanislav Moshkalev ; Victor Sonnenberg
Associated grant(s):13/13231-0 - 28th Symposium on Microelectronics Technology and Devices, AR.BR
13/02572-1 - 223rd Electrochemical Society Meeting, AR.EXT
12/14204-4 - IEEE International SOI Conference, AR.EXT
+ associated grants 12/11996-7 - Modeling of nanometric transistors for applications in analog circuits, AV.EXT
12/11991-5 - SBMicro 2012 - 27th Symposium on Microelectronics Technology and Devices, AR.BR
12/11519-4 - SBMicro 2012 - 27th Symposium on Microelectronics Technology and Devices, AR.BR
12/10818-8 - SBMicro 2012 - 27th Symposium on Microelectronics Technology and Devices, AR.BR
09/01617-6 - 215th ECs Meeting, AR.EXT - associated grants
Associated scholarship(s):13/13690-5 - Study of SOI MOSFETs transistors with ultra-thin silicon film body and buried oxide at high temperatures, BP.DR
12/12700-4 - Analytical Models for Static Electric Behaviour of FinFETs, BP.DR
12/07778-4 - Theoretical and Experimental Study of the Tunneling Field Effect Transistors (TFET), BP.PD
11/03864-0 - Study of proton radiation effects in SOI MOSFETs multiple gates transistors, BP.MS
10/20699-0 - Study of the Noise and the Current Switch-off Transient in Multiple Gate Transistors, BP.PD
10/09509-5 - Characterization of Ultrathin Layers of High Dielectric Constant and Application in the Fabrication of High Performance MOS Structures, BP.PD
10/00537-6 - Operation and Modeling of Junctionless MOSFETs in Cryogenic Environments, BP.DR - associated scholarships


The goal of this project is the design, fabrication and electrical characterization of multiple gate transistors with vertical channel built on silicon-on-insulator substrate, known as FinFET. These devices are the most promising structures for the next technological generation on CMOS integrated circuits fabrication. To achieve this objective, it is being proposed a thematic network formed by Escola Politécnica da USP (São Paulo), Centro de Componentes Semicondutores (CCS) UNICAMP (Campinas) and Centro Universitário da FEI (São Bernardo do Campo). The steps of design and fabrication will be performed by USP and UNICAMP, while in the electrical characterization FEI will also take care together with them. The devices modeling will be developed by FEI. The new FinFET´s to be designed and fabricated in Brazil (USP/UNICAMP) in this project will be based in the preliminary version developed in NAMITEC project (CNPq - Instituto do Milênio - process n. 420031/2005-7). During the electrical characterization, FinFET´s fabricated at USP/UNICAMP will be used as well as the devices fabricated at IMEC (Interuniversity Microelectronics Center, Leuven, Bélgica). Through the results obtained experimentally as well as three-dimensional simulation, the main electrical parameters from FinFET´s will be analyzed in digital and analogical circuits applications, such as threshold voltage, subthreshold slope, transconductance, transconductance over drain current ratio, Early voltage and intrinsic gain voltage. These parameters will be studied not only at room temperature, but also in the 80K to 730K ranges, for aerospace applications. The success of this work will allow Brazil to enter in the world of nanotechnology, fundamental step to the technological evolution. (AU)

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