ADAPTT: providing resource efficiency in traffic classification through the synergistic and adaptive use of FPGAs and CNNs

Abstract

Deeper neural networks and, more specifically, convolutional (CNN) ones, have been shown to be a highly accurate solution to deal with Internet Traffic classification, contributing to the improvement of capacity planning, efficient resource management, detection of anomalies and many more. However, to handle the significant increase in traffic volume, efficient processing is mandatory, with low latency and high throughput. Thus, FPGAs appear as an emerging and increasingly popular alternative due to their ability to reconfigure and adapt. FPGAs allow specific optimizations through High Level Synthesis (HLS), which generates several circuits from the same description and with different characteristics. In this same scenario, CNN models can also be improved, through pruning and quantization, which aim to reduce the amount of memory or processing power required, with minimal losses in accuracy. Thus, this project proposes the ADAPTT - An Adaptive Deep Learning FPGA APproach for Traffic ClassifiesTion, with the objective of increasing the efficiency (i.e. throughput, energy, use of resources, accuracy or cost of implementation) in the execution of CNNs in FPGA accelerators for traffic control. ADAPTT involves two steps: 1) Static: It creates, at design time and automatically through the intelligent use of heuristics, a library with several configurations, composed of HLS-enhanced versions of accelerators for FPGA and with optimized models of CNNs generated from pruning and quantization, resulting in different profiles regarding throughput, energy consumption, accuracy etc.; and 2) Dynamic: which, after the system is up and running, can adapt through the dynamic change of its configurations, given an optimization goal (e.g. low energy consumption, high throughput or accuracy) and current state of the system (e.g., traffic volume or minimum accuracy required), taking advantage of the intrinsic reconfigurability of the FPGA. (AU)