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Runtime reconfigurable hardware platform model

Abstract

Today, it is getting harder and harder to come up with new performance enhancements in the computer architecture area when compared to the period of about 50 years ago. This is mainly due to the end of Dennard's scaling and to the slow down of Moore's law. In this sense, the application of domain-specific architectures (DSA) becomes an interesting alternative. Unlike general-purpose architectures, the hardware can be specific and optimized in runtime for a specific domain with DSA. In this context, it is necessary to consider new approaches to the design of embedded systems, such as adaptive support along with DSA. However, notice that embedded system designs highly depend on a hardware platform since the specification and conception project's phases. The possibility of having a hardware platform model, at a high level of abstraction, that could be mapped to a low level of abstraction present itself as a research area and a challenge to be conquered. Thus, the objective of this research focuses on the study and analysis of models of computation, domain ontology, and reconfigurable processors to propose a runtime reconfigurable hardware platform model considering two minimum levels of abstraction: specification level and implementation level. The main contribution to embedded systems and reconfigurable computing will be the possibility to design and specify the system focusing on the functions and requirements that such a system must provide, thus obtaining an executable model. With such a model it will be possible to "execute the specification", i.e. to simulate the system at a high level of abstraction before moving to the implementation phase. (AU)

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Scientific publications
(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)
LOUBACH, DENIS S.; BONNA, RICARDO; UNGUREANU, GEORGE; SANDER, INGO; SODERQUIST, INGEMAR. Classification and Mapping of Model Elements for Designing Runtime Reconfigurable Systems. IEEE ACCESS, v. 9, p. 156337-156360, . (19/27327-6)

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