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Atomistic simulation of nanowire MOSFETs electrical properties

Grant number: 19/15500-5
Support Opportunities:Regular Research Grants
Duration: January 01, 2020 - March 31, 2023
Field of knowledge:Engineering - Electrical Engineering - Electrical Materials
Convênio/Acordo: CONFAP - National Council of State Research Support Foundations
Principal Investigator:Marcelo Antonio Pavanello
Grantee:Marcelo Antonio Pavanello
Host Institution: Campus de São Bernardo do Campo. Centro Universitário da FEI (UNIFEI). Fundação Educacional Inaciana Padre Sabóia de Medeiros (FEI). São Bernardo do Campo , SP, Brazil
Associated researchers: Alan Carlos Junior Rossetto ; Fábio Fedrizzi Vidor ; Michelly de Souza ; Renan Trevisoli Doria ; Rodrigo Trevisoli Doria ; Thiago Hanna Both ; Vinícius Valduga de Almeida Camargo


The semiconductor industry owes much of its success to the ability of continually downscale the devices (basically transistors) that make the integrated circuits (chips). This decrease in the size of the devices allows an increase in the number of transistors integrated in a single chip. It also allows the reduction of the dissipated power, larger memories and integration of new functionalities to the chip. As a way to minimize the degradation of the electrical properties of the MOS transistors due to miniaturization, MOS structures with multiple gates are now used, since they significantly improve the electrostatic control of the charges in the channel region. Multiple-gate transistors have gained a lot of attention from the scientific community. Another multiple-gate structure, recently developed and that has presented promising results, is the nanowire MOS transistor. These structures have a cross section of few nanometers, allowing excellent electrostatic control and minimizing undesirable effects in MOS transistors with channel lengths of the order of 10 nanometers. In transistors with nanometer dimensions, a single atom or electron can influence the electrical behavior of the transistor. Technologically, it is impractical or extremely difficult to control the manufacturing process of semiconductors on an atomic scale. Thus, it is more appropriate to realize the design of integrated circuits in order to tolerate variations in the electrical behavior of the transistors that compose it. For that, models and simulators are needed that can predict the electric behavior and the associated variations. Therefore, simulation models and techniques should consider this new stochastic nature of transistor behavior. The materials used have imperfections, defects or traps that can capture electrons that should contribute to the conduction of electric current. This leads to reliability problems, since the behavior of these traps can lead to a change in the performance and response of the electric circuit over time. A problem for the simulation of nanometer size MOS structures is the need to include quantum effects, which modify the centroid of electrons to the depth of the semiconductor, a few nanometers below the interface between the silicon and the door insulation. In these cases, commercial numerical simulation tools, which are based on the semi-classical approach of electric current conduction by the diffusion and drift mechanisms, do not allow the inclusion of these effects with precision. One way to perform simulations that are more realistic is the adoption of atomistic (or particle) simulation tools. In these tools, the electric current scattering events are determined probabilistically, without the initial assumption of conduction by the diffusion and drift mechanisms. In this context, a three-dimensional simulator of Monte Carlo devices, based on non-isothermal particles, was developed in a collaboration between the groups participating in this proposal, which is fully functional for planar structures. This collaborative research project aims to enhance the atomistic simulation tool, enabling it to simulate nanowire MOS transistors. The results of the atomistic simulations will be compared with experimental results, deepening the knowledge about the electrical properties of nanowires MOS transistors, when submitted to conditions of variable temperature. For validation of the atomistic simulator, electrical measurements will be used nanowires MOS transistors. Three-dimensional numerical simulations using semi-classical techniques will also be used for comparison with atomistic simulations. (AU)

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Scientific publications (6)
(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)
GRAZIANO JUNIOR, NILTON; COSTA, FERNANDO J.; TREVISOLI, RENAN; BARRAUD, SYLVAIN; DORIA, RODRIGO T.. Influence of interface traps density and temperature variation on the NBTI effect in p-Type junctionless nanowire transistors. Solid-State Electronics, v. 186, . (19/15500-5)
RIBEIRO, THALES AUGUSTO; BERGAMASCHI, FLAVIO ENRICO; BARRAUD, SYLVAIN; PAVANELLO, MARCELO ANTONIO. Influence of fin width variation on the electrical characteristics of n-type junctionless nanowire transistors at high temperatures. Solid-State Electronics, v. 185, . (16/10832-1, 19/15500-5)
DE SOUZA, MICHELLY; DORIA, RODRIGO T.; TREVISOLI, RENAN; BARRAUD, SYLVAIN; PAVANELLO, MARCELO A.. On the Application of Junctionless Nanowire Transistors in Basic Analog Building Blocks. IEEE TRANSACTIONS ON NANOTECHNOLOGY, v. 20, p. 234-242, . (19/15500-5, 14/18041-8)
COSTA, FERNANDO J.; TREVISOLI, RENAN; DORIA, RODRIGO T.. Thermal cross-coupling effects in side-by-side UTBB-FDSOI transistors. Solid-State Electronics, v. 185, . (19/15500-5)
RIBEIRO, THALES AUGUSTO; BARRAUD, SYLVAIN; PAVANELLO, MARCELO ANTONIO. Analysis of the Electrical Parameters of SOI Junctionless Nanowire Transistors at High Temperatures. IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, v. 9, p. 492-499, . (16/10832-1, 19/15500-5)
MARINIELLO, GENARO; DE CARVALHO, CESAR AUGUSTO BELCHIOR; PAZ, BRUNA CARDOSO; BARRAUD, SYLVAIN; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO. Analog characteristics of n-type vertically stacked nanowires. Solid-State Electronics, v. 185, . (19/15500-5)

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