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Performance optimizations for multicore architectures


Multicore machines are ubiquitous nowadays and the tendency is for semiconductor companies to keep adding more and more cores into their new microprocessors. Unfortunately, support for programming these highly parallel machines have not kept pace and we are left with underutilized computer systems. The big challenge facing the industry today is how to ease the life of programmers in writing parallel code by creating adequate software and hardware. What makes parallel programming so hard is that programmers are faced with two simultaneous demanding goals: the code must be correct and efficient, both performance and energy-wise, as the number of cores per chip scales. Writing parallel code is not hard per se, but writing parallel code that can achieve high performance and scalability is far from trivial.In a broad sense, this research project aims at investigating performance optimizations for multicore microprocessors so that programmers can more easily write parallel code and still benefit from current multicore machines. In particular, this project seeks to investigate optimization opportunities both at the programmer level, by providing diagnostic and profiling tools along with powerful language constructs, and at the code level, by devising optimization techniques for compilers and runtime. A clear contribution of this proposal is to enable average programmers to make the most out of current multicore-based systems, as well as to deliver automatic techniques to improve performance of parallel code. (AU)

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(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)
BALDASSIN, ALEXANDRO; BARRETO, JOAO; CASTRO, DANIEL; ROMANO, PAOLO. Persistent Memory: A Survey of Programming Support and Implementations. ACM COMPUTING SURVEYS, v. 54, n. 7, . (19/10471-7, 18/15519-5)

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